dsp 5 6f8 0 2pb / d r e v . 0 , 1 / 2002 ? m o t o r o l a , i n c . , 2 0 0 2 . a l l r i g h t s r e s e r v e d. dsp56f802 p r o d uc t brief dsp56f80 2 1 6-bi t digita l signa l p r o cessor ? u p t o 4 0 m i p s o p e r a t i o n a t 8 0 m h z c o r e fr e que n cy ds p a n d m c u fu n c t ion a l i t y i n a u n if i ed, c - ef f i c i e n t a r c h i t e c t u r e mcu-fr i en d l y ins t ruc t io n s e t s u ppor t s bo t h ds p a n d c on t rol l e r fu n c t ion s : mac , b it m a n i pul a t i o n uni t , 1 4 a d dre s s i n g mod e s 8 k 1 6 -bi t wo r d s prog r a m f l a s h 1 k 1 6 -bi t wo r d s prog r a m r a m 2 k 1 6 -bi t wo r d s d a t a fl a s h 1 k 1 6 -bi t wo r d s d a t a ram 2 k 1 6 -bi t wo r d s b o o t fla s h h a rdwa r e d o a n d r e p lo o ps 6 - ch a nn e l p w m modu l e t w o 12- b i t adc s ( 1 x 2 c h ann e l , 1 x 3 c han n e l ) s e ri a l com m u n i c a t ion s int e rf a c e (s c i) t w o g e n e ra l pur p os e qua d t im e r s wi t h 2 e x t e r n a l p i n s j t ag/on c e tm po r t fo r de b uggi n g on - ch i p r el a x a ti o n o s c i l l a tor 3 2 -pi n l q f p pa c ka g e 4 s h a r e d g p i o fi g u r e 1 . ds p 56 f 80 2 bloc k diag r am j t a g / o n c e po r t d i g i ta l r e g a na l o g reg lo w v o l t age s upe r v i s o r p r o g r a m cont r o l l er and ha r d w a r e l oop i n g un i t da t a a lu 1 6 x 1 6 + 3 6 3 6 - bi t m ac t h r e e 16 - b i t i n pu t reg i s te r s t w o 36 - b i t a c c um u l ato r s a d d r e s s g ene r at i on un i t b i t ma n i pu l at i on un i t p l l c l o c k g en o r o pt i on a l inte r nal re l a x a t i o n o s c . 16 - b i t d s p 5 6 8 00 core p a b p d b x d b2 c g db x ab1 x ab2 g p i o b 3/ x t a l g p i o b 2/ e x t a l int e rru p t c o n t r o ls i p b b c o ntr o l s ipb u s br i dge ( i pbb) m o d u l e c o n t r o l s a ddr e s s b u s [8:0] d a t a bu s [15:0] c o p r es e t r es e t ir q a a ppl i c a ti o n- sp e c i fic m e m o r y & p e rip h er a ls inte r r upt cont r o l l er p r og r a m mem o r y 818 8 x 1 6 f l a s h 102 4 x 1 6 sr a m bo o t f l ash 204 8 x 1 6 f l a s h da t a memo r y 204 8 x 1 6 f l a s h 102 4 x 1 6 sr a m c o p / w at c hdog s c i 0 or gp i o q ua d t i me r d o r g p io q ua d t i me r c a / d 1 a / d 2 a d c 2 2 3 2 6 p w m o utputs p w m a 16 16 v c a p c v dd v ss *v d d a v ssa 5 2 2 3 ? ? ? ? ? ? ? ? v r ef * i n c l ude s t c s p i n wh i c h i s r e s e r v e d fo r f a c to r y u s e an d i s t i e d t o v ss f a u l t a 0
2 dsp56f802 product brief motorola dsp56800 digital signal processing core features efficient 16-bit dsp56800 family dsp engine with dual harvard architecture as many as 40 million instructions per second (mips) at 80 mhz core frequency single-cycle 16 16-bit parallel multiplier-accumulator (mac) two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter parallel instruction set with unique dsp addressing modes hardware do and rep loops three internal address buses and one external address bus four internal data buses and one external data bus instruction set supports both dsp and controller functions controller style addressing modes and instructions for compact code efficient c compiler and local variable support software subroutine and interrupt stack with depth limited only by memory jtag/once debug programming interface dsp56f802 memory features harvard architecture permits as many as three simultaneous accesses to program and data memory on-chip memory including a low cost, high volume flash solution ?8k 16 bit words of program flash ?1k 16-bit words of program ram ?2k 16-bit words of data flash ?1k 16-bit words of data ram ?2k 16-bit words of bootflash programmable bootflash supports customized boot code and field upgrades of stored code through jtag interface dsp56f802 peripheral circuit features pulse width modulator (pwm) with six pwm outputs with deadtime insertion; supports both center- and edge-aligned modes two12-bit,analog-to-digitalconverters(adcs),1x2channeland1x3channel,whichs upport two simultaneous conversions with a total of five inputs; adc and pwm modules can be synchronized general purpose quad timers with two extra pins (or two addidtional gpio lines) serial communication interface (sci) with two pins (or two gpio) four multiplexed general purpose i/o (gpio) pins computer-operating properly (cop) watchdog timer external reset pin for hardware reset trimmable on-chip relaxation oscillator
motorola dsp56f802 product brief 3 jtag/on-chip emulation (once?) for unobtrusive, processor speed-independent debugging software-programmable, phase lock loop-based frequency synthesizer for the dsp core clock energy information fabricated in high-density cmos with 5v tolerant, ttl-compatible digital inputs uses a single 3.3v power supply on-chip regulators for digital and analog circuitry to lower cost and reduce noise integrated power supervisor wait and stop modes available dsp56f802 description the dsp56f802 is a member of the dsp56800 core-based family of digital signal processors (dsps). it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, the dsp56f802 is well-suited for many applications. the dsp56f802 includes many peripherals that are especially useful for applications such as: motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, and industrial control for power, lighting, automation. the dsp56800 core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. ?best in class? development environment the sdk (software development kit) provides fully debugged peripheral drivers, libraries and interfaces that allow programmers to create their unique c application code independent of component architecture. the codewarrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) and development system cards support concurrent engineering. together, the sdk, codewarrior, and evms create a complete, scalable tools solution for easy, fast, and efficient development. product documentation the four documents listed in table 1 are required for a complete description and proper design with the dsp56f802. documentation is available from local motorola distributors, motorola semiconductor sales offices, motorola literature distribution centers, or online at www.motorola.com/semiconductors/dsp.
DSP56F802PB/d motorola and the stylized m logo are registered in the us patent & trademark office. all other product or service names are the property of their respective owners. ? motorola, inc. 2002. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1?303?675?2140 or 1?800?441?2447 japan: motorola japan ltd.; sps, technical information center, 3?20?1, minami?azabu. minato?ku, tokyo 106?8573 japan. 81?3?3440?3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. 852?26668334 technical information center: 1?800?521?6274 home page: http://www.motorola.com/semiconductors/ motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee r egarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or c ircuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may b eprovidedinmotorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, inc luding ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent ri ghts nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation wh ere personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hol d motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonabl e attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. table 1. dsp56f802 chip documentation ordering information consult a motorola semiconductor sales office or authorized distributor to order parts. topic description order number dsp56800 family manual detailed description of the dsp56800 family architecture, and 16-bit dsp core processor and the instruction set dsp56800fm/d dsp56f80x user?s manual detailed description of memory, peripherals, and interfaces of the dsp56f801, dsp56f802, dsp56f803, dsp56f805, and dsp56f807 dsp56f801-7um/d dsp56f802 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions dsp56f802/d dsp56f802 product brief summary description and block diagram of the dsp56f802 core, memory, peripherals and interfaces (this document) DSP56F802PB/d table 2. dsp56f802 ordering information part supply voltage package type pin count frequency (mhz) order number dsp56f802 3.0?3.6 v plastic quad flat pack (lqfp) 48 80 dsp56f802fa80
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